Efforts to integrate more on-die memory, that is, larger caches, with a microprocessor are guided by the premise that to do so is a power-efficient means of achieving better performance. For example, the area used by six transistor (6T) SRAM cells, which are typically used in large caches, is limited by constraints on die size and to limit manufacturing costs. Thus, a key to enabling larger caches is minimizing the additional cost of incorporating a denser memory cell than SRAM.
One transistor—One Capacitor (1T-1C) DRAM cells have been proposed. These DRAM cells strive to be ten times smaller in area than traditional SRAM cells. The design goals for these DRAM cells need to account for the greater costs involved in making a capacitor that can store enough charge to maintain reasonable refresh times. For example, capacitances at least of 25 fF are calculated to be required.
The recent work in DRAM gain cells has sought to fabricate cells using standard complementary metal oxide semiconductor (CMOS) processes. Such cells may be less expensive to manufacture and more scalable to future device technologies than the SRAM cells, since they do not need a fixed capacitor value. With these goals in mind, it is, therefore, desirable to devise an integrated DRAM that provides for larger memory caches without additional process complexity or costs.
It should be understood that these figures depict embodiments of the invention. Variations of these embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, the flow charts contained in these figures depict particular operational flows. However, the functions and steps contained in these flow charts can be performed in other sequences, as will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.